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dc.creatorLuković, Vanja
dc.creatorKrneta, Radojka
dc.creatorDamnjanović, Đorđe
dc.creatorPeulić, Aleksandar
dc.date.accessioned2021-09-24T15:37:26Z
dc.date.available2021-09-24T15:37:26Z
dc.date.issued2017
dc.identifier.issn2376-631X
dc.identifier.urihttps://gery.gef.bg.ac.rs/handle/123456789/831
dc.description.abstractThe application of remote lab "Nexys 2 FPGA platform" for learning digital circuits design is described in this paper. The experiment requires installation of Xilinx ISE Design Suite software on students' PCs for designing digital circuits and generating. bit file. There are three ways of designing digital circuits in Xilinx ISE Design Suite software: by programming in VHDL language, by programming in Verilog language or by using schematic diagrams. Working environment of the remote lab consists of Digilent Nexys 2 FPGA platform that is connected with PC. Students connect with the remote lab PC through CEyeClon viewer which also needs to be installed on their PCs together with. Net Framework 4.5. Generated. bit file is loaded through Digilent Adept2 software that is installed on the remote lab PC and used for the FPGA programming. The usage of this experiment enable engineering students to achieve practical experiences and skills for designing and simulating digital circuits using FPGA and to better understand and learn theory of designing digital circuits.en
dc.publisherIEEE, New York
dc.relationEducation, Audiovisual and Culture Executive Agency (EACEA) [543667-TEMPUS-1-2013-1-RS-TEMPUS-JPHES]
dc.rightsrestrictedAccess
dc.sourceProceedings of 4th Experiment"International Conference (EXP.At'17)
dc.subjectdesigningen
dc.subjectsimulatingen
dc.subjectdigital circuitsen
dc.subjectNexys 2 platformen
dc.subjectremote experimenten
dc.subjectFPGAen
dc.subjectXilinx ISE Design Suiteen
dc.titleThe remote lab "Nexys 2 FPGA platform" aimed for learning design of digital circuitsen
dc.typeconferenceObject
dc.rights.licenseARR
dcterms.abstractКрнета, Радојка; Пеулић, Aлександар; Дамњановић, Ђорђе; Луковић, Вања;
dc.citation.spage101
dc.citation.epage102
dc.citation.other: 101-102
dc.identifier.wos000412842600022
dc.identifier.scopus2-s2.0-85027848069
dc.identifier.rcubhttps://hdl.handle.net/21.15107/rcub_gery_831
dc.type.versionpublishedVersion


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